In semi-conductor devices, in particular in memory devices such as DRAMs (DRAM=Dynamic Random Access Memory and/or dynamic read/write memory) based on CMOS technology, so-called clock signals are used for the chronological co-ordination of the processing or relaying of the data.
Conventional semiconductor devices in general use a single clock signal present on a single line (i.e. a so-called “single-ended” clock signal), for this purpose.
The data may then, for instance, be relayed at the respective rising edge of the single-ended clock signal (or, alternatively, e.g. at the respective falling edge of the single-ended clock signal).
Further, so-called DDR devices, in particular DDR-DRAMs (DDR-DRAM=Double Data Rate DRAM) are already known in prior art.
In DDR devices—instead of one single clock signal present on a single line (“single ended” clock signal)—two differential, oppositely inverse clock signals present on two separate lines are used.
Every time, for instance, when the first of the two clock signals changes from a “logic high” state (e.g. a high voltage level) to a “logic low” state (e.g. a low voltage level), the second clock signal—substantially simultaneously—changes its state from “logic low” to “logic high” (e.g. from a low to a high voltage level).
Conversely, whenever the first clock signal changes from a “logic low” state (e.g. a low voltage level) to a “logic high” state (e.g. a high voltage level), the second clock signal (again substantially simultaneously) changes its state from “logic high” to “logic low” (e.g. from a high to a low voltage level).
With DDR devices, the data are, in general, relayed both at the rising edge of the first clock signal and at the rising edge of the second clock signal (or both at the falling edge of the first clock signal and at the falling edge of the second clock signal).
This means that data are relayed more frequently and/or faster (in particular twice as frequently and/or twice as fast) in a DDR device than in corresponding, conventional devices using a “single ended” clock signal, i.e. the data rate is higher, in particular twice as high, as that of corresponding, conventional devices.
The clock signal (“DQS” or “data strobe” signal) used internally in the device for the chronological coordination of the processing and/or relaying of the data (or—when differential, oppositely inverse clock signals are used—the internal clock signal DQS and the clock signal BDQS that is oppositely inverse to the clock signal DQS) has to be synchronous to a clock signal (“clk” or “clock” signal) input externally into the device (or synchronous to the differential clock signals clk, bclk input externally into the device, respectively).
The external clock signal(s) clk, bclk is (are) generated by an appropriate clock signal generator that is connected to the device.
For synchronizing the internally generated clock signal DQS or the internally generated clock signals DQS, BDQS, respectively, with the external clock signal(s) clk, bclk, a clock signal synchronizing device, e.g. a DLL circuit (DLL=Delay Locked Loop) is used. Such a circuit is, for instance, known form EP 964 517.
A clock signal synchronizing device may e.g. comprise a first delay means into which the external clock signal(s) clk, bclk is/are input, and which loads the input clock signal(s)—depending on a control signal output by the phase comparator—with a variable delay time tvar that is adjustable by the control signal.
The signal(s) output by the first delay means may be used—internally—in the device for the chronological coordination of the processing and/or relaying of the data (i.e. as—internal—clock signal(s) DQS or BDQS).
The signal DQS output by the first delay means is fed to a second delay means that loads the input signal DQS with a—fixed—delay time tconst that corresponds approximately to the sum of the signal delays caused by the receiver(s) (“receiver delay”), the respective data path (“data path delay”), and the off-chip driver(s) (“OCD delay”).
The signal (FB signal or “feedback signal”) output by the second delay means is fed to the above-mentioned phase comparator. There, the phasing of the FB signal is compared with the phasing of the clk signal that is also input in the phase comparator 4. Depending on whether the phase of the FB signal is faster or slower than that of the clk signal, the phase comparator outputs—as a control signal for the above-mentioned first delay means—an incrementing signal (INC signal) or a decrementing signal (DEC signal), said signals having the effect that the delay tvar of the clk signal caused by the first signal delay means is increased in the case of an INC signal and decreased in the case of a DEC signal, so that, finally, the clk signal and the FB signal are synchronized, i.e. the clock signal synchronizing device is “locked”.
In particular at high frequencies, there can be relatively strong distortions of the clock signal clk—that is provided by the above-mentioned external clock signal generator—(or of the—externally provided, differential—clock signals clk, bclk, respectively). These result, for instance, in that the “logic low” state of the clk signal is e.g. shorter (or e.g. longer) than the “logic high” state of the clk signal (and e.g. the “logic low” state of the bclk signal is e.g. longer (or e.g. shorter) than the “logic high” state of the bclk signal). Consequently, the—internal—clock signal DQS or BDQS obtained by the above-mentioned clock signal synchronizing device, e.g. the DLL circuit, from the external clock signal clk or bclk is also relatively strongly distorted.